← Back to selected work ANALOG / SRAM / INDIVIDUAL PROJECT / Documented project

Low-Power SRAM Sense Amplifier

A documented study of StrongARM, Double-tail, and Preamp-assisted StrongARM topologies under SRAM-style small-swing sensing.

StrongARM SRAM sense amplifier schematic

My role

Author and designer of the core sense-amplifier study, testbench, simulation, and comparison reported in the document.

Project visuals

Preamp-assisted StrongARM topology overview — Preamp-assisted path with separated timing and output latch.

Sense amplifier waveform comparison from the report — Waveform evidence is interpreted with the report's polarity and pass criteria.

Measured results

StrongARM MC decision yield99.8% / 95.0% / 71.8%DVBL 50 / 30 / 10 mV; 500 samples; Errors=0

PA4 MC decision yield98.8% / 30 mVVDD 0.8 V; POL=1; 500 samples; Errors=0

StrongARM PVT point0.7 V / 50 mVBaseline final sizing; checked corners

PA4 nominal at 10 mV270.1 ps / 13.72 fJVDD 0.8 V; POL=1; MC yield 59.6%

Design objectives

Characterize a StrongARM SRAM sense amplifier with nominal, VDD, PVT, and Monte-Carlo analysis.
Study Double-tail Dynamic Latch as a secondary direction and record why it was not selected as the main topology.
Develop and size a Preamp-assisted StrongARM with NAND SR-latch, keeping nominal pass separate from robustness.

Implementation approach

Cadence Virtuoso/ADE with Spectre and GPDK45nm were used for schematic-level characterization. BL/BLB are modeled near VDD with a small DVBL, and the report separates nominal, PVT, and 500-sample mismatch yield.

Scope and limitations

This is a schematic-level core sense-amplifier study with idealized bitline sources. The PA4 final sizing has no complete PVT rerun in the report, and its 10 mV Monte Carlo yield is 59.6%. No full SRAM array or extracted layout is claimed.