First principles
Starting with digital logic, analog circuits, and the questions underneath both.
Integrated Circuit Design / HCMUT
ENGINEERINGTHE INVISIBLE.
Exploring digital systems, CMOS fundamentals, and the patient journey from logic to silicon.
SILICON CORE / 001
HTP / IC-01
TRACE ACTIVEArtistic silicon study
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01The human behind the logic
Every complex system starts with a simple question.
I am a fourth-year Integrated Circuit Design student at HCMUT, learning to move carefully between abstraction and implementation.
My work spans digital and analog circuits, CMOS fundamentals, RTL design flow, and EDA-based simulation. I care about understanding why a design behaves the way it does, then communicating that reasoning clearly.
I am looking for an internship where I can keep learning, contribute with precision, and grow closer to the semiconductor industry.
Start a conversation ↗BaseHCMUTVNU-HCM / VIETNAM
FocusIntegrated Circuit DesignDIGITAL + ANALOG
GPA3.2ACADEMIC RECORD
02My technical universe
Thinking in systems.
A growing toolkit for turning questions into circuits, simulations, and decisions.
01 / DIGITAL
Digital design
From logic fundamentals to RTL thinking: translating behavior into synchronous, testable structures.
- Digital circuits
- SystemVerilog (basic)
- RISC-V exposure
- RTL design flow
Select a node to trace the signal04 / 04
03Selected work / measured progress
Studies in motion.
Three documented projects, with methods, results, and the limits of each claim.
01 / 03DIGITAL DESIGN / TEAM PROJECTAcademic project
8×8 Register Bank with Clock Gating
A documented team project for an 8-register × 8-bit bank with one write port, one read port, and a latch-based Integrated Clock Gating path.
02 / 03ANALOG / SRAM / INDIVIDUAL PROJECTDocumented project
Low-Power SRAM Sense Amplifier
A documented study of StrongARM, Double-tail, and Preamp-assisted StrongARM topologies under SRAM-style small-swing sensing.
03 / 03ANALOG / RF SYSTEMS / TEAM PROJECTCourse project
2.4 GHz PLL with Dual-Modulus Divider
A TSMC 180 nm schematic-level PLL project targeting 2.4 GHz, a 1 MHz step, and a total divide ratio N=2400.
STATUS NOTE
Measurements below are tied to the conditions reported in the project documents. A result is useful only when its test context travels with it.
04My path to silicon
From curiosity
to circuitry.
A timeline without inflated milestones — just the next useful question, and the work that follows it.
Learning the language
Exploring SystemVerilog, RISC-V architectures, and RTL design flow.
Seeing the trade-offs
Moving into CMOS, VLSI laboratories, and EDA-based simulation.
Building in public
Turning academic projects into clear engineering stories and repeatable habits.
05The human side
Beyond the schematics.
Behind each circuit is a way of working: clarify the conditions, show the reasoning, and keep learning.
Question the result
I read measurements alongside their test conditions before drawing a conclusion.
Make reasoning visible
Diagrams, waveforms, and notes help explain how a design behaves and where its limits are.
Keep learning
I am building breadth across digital and analog design to contribute on an engineering team.
06Open channel
Let's build
what's next.
Open to opportunities in IC design, RTL development, analog circuits, and verification.